The present invention relates generally to processors, and, more particularly, to correction of soft errors that may occur in sleeping processors.
In low power applications, processors (e.g., microprocessors) are often put into a low-voltage sleep mode when they go idle after completing a function. During this period of time, and especially in processors built with deeply scaled technologies, there is an increasing risk for radiation-induced (i.e., “soft”) errors to occur in the registers and latches holding the processor machine state data. In memory this is not a problem as encoded data can be stored along with the actual word to later perform error detection when that word is retrieved from memory. But within the processor logic, the bits that comprise each of the stored register words heretofore have had no error checking applied thereto.